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半导体学报（英文版）
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2026年9期
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Yield-aware optimization of memory gate length in split-gate SONOS:trade-off between erase efficiency and lithography process window
Yield-aware optimization of memory gate length in split-gate SONOS:trade-off between erase efficiency and lithography process window
摘要
A yield-aware optimization strategy is proposed to address thetrapped charge mismatch effect(TCME)in split-gate SONOS flash by bridging device physics with lithography constraints.The study demonstrates that scaling the memory gate length(LMD)induces a lateral field extension that physically minimizes the region of residual trapped electrons.However,a fun-damental physics-lithography trade-off is identified:while aggressive scaling maximizes erase efficiency,process variation band(PVB)analysis mandates a 50 nm manufacturable optimum to maintain critical dimension(CD)variation within the 10%safety threshold.Experimental verification on an 8 Mb array confirms the strategy's effectiveness,achieving 99.3%yield and suppress-ing bit-to-bit disturbance to 10.9%of the memory window(MW).Supported by endurance exceeding 105 cycles,these results demonstrate a viable high-yield pathway for scaling high-reliability memories.
年，卷(期)：
2026, 47(9)
机标分类号：
TP333
TH137
TP273
在线出版日期：
2026年10月12日
